<!-- 
    DDR3L Unbuffered SODIMM Information:
    
    Part Number: M471B5674QH0-YH9/K0
    Density: 2GB
    Organization: 256Mx64
    Component Composition: 256Mx16(K4B4G1646Q-HY##)*4
    Number of Rank: 1
    
    Device mounted: K4B4G1646Q-HYK0
    Original fck is 800 MHz (DDR3-1600). Adapted to fck 533 MHz (DDR-1066).
    Deepak provided most of the timing and current values. For the ones not provided datasheet values were used.


    2GB x64 DIMM with: 4 * 4Gb x16 devices (K4B4G1646Q-HYK0) with Page Size: 2KB

    DIMM Characteristics:
    Byte Offset (Y): 8    [0:2]   (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
    Cols        (C): 1K   [3:12]  (A0 - A9)   -> 10 bit
    Rows        (R): 32K  [13:27] (A0 - A14)  -> 15 bit
    Bank        (B): 8    [28:30] (BA0 - BA2) -> 3  bit

    3 2 2 | 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 
    0 9 8 | 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
    B B B | R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->

<addressmapping>
    <channel from="128" to="128" /> <!-- workaround to have only one channel -->
    <bank    from="28"   to="30" />
    <row     from="13"   to="27" />
    <column  from="3"    to="12" />
    <bytes   from="0"    to="2"  />
</addressmapping>

