<!-- 
    DIMM Characteristics:
    Bank        (B): 8    [30:32] (BA0 - BA2) -> 3  bit
    Rows        (R): 128K [13:29] (A0 - A16)  -> 17 bit
    Cols        (C): 1K   [3:12]  (A0 - A9)   -> 10 bit
    Byte Offset (Y): 8    [0:2]   (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit

    3 3 3 | 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 
    2 1 0 | 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
    B B B | R R R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->

<addressmapping>
    <channel from="128" to="128" /> <!-- workaround to have only one channel -->
    <bank    from="30"   to="32" />
    <row     from="13"   to="29" />
    <column  from="3"    to="12" />
    <bytes   from="0"    to="2"  />
</addressmapping>

