/*
 * Copyright (c) 2015, University of Kaiserslautern
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived from
 *    this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors:
 *    Janik Schlemminger
 *    Robert Gernhardt
 *    Matthias Jung
 */

#ifndef EXTENDED_PHASE_DRAM
#define EXTENDED_PHASE_DRAM

// DRAM Control Phases
DECLARE_EXTENDED_PHASE(BEGIN_PREB);
DECLARE_EXTENDED_PHASE(END_PREB);

DECLARE_EXTENDED_PHASE(BEGIN_PRE);
DECLARE_EXTENDED_PHASE(END_PRE);

DECLARE_EXTENDED_PHASE(BEGIN_PRE_ALL);
DECLARE_EXTENDED_PHASE(END_PRE_ALL);

DECLARE_EXTENDED_PHASE(BEGIN_ACTB);
DECLARE_EXTENDED_PHASE(END_ACTB);

DECLARE_EXTENDED_PHASE(BEGIN_ACT);
DECLARE_EXTENDED_PHASE(END_ACT);

DECLARE_EXTENDED_PHASE(BEGIN_REFA);
DECLARE_EXTENDED_PHASE(END_REFA);

DECLARE_EXTENDED_PHASE(BEGIN_REFB);
DECLARE_EXTENDED_PHASE(END_REFB);


// Phases for Read and Write
DECLARE_EXTENDED_PHASE(BEGIN_WR);
DECLARE_EXTENDED_PHASE(END_WR);

DECLARE_EXTENDED_PHASE(BEGIN_RD);
DECLARE_EXTENDED_PHASE(END_RD);

DECLARE_EXTENDED_PHASE(BEGIN_WRA);
DECLARE_EXTENDED_PHASE(END_WRA);

DECLARE_EXTENDED_PHASE(BEGIN_RDA);
DECLARE_EXTENDED_PHASE(END_RDA);

// Phases for Power Down
DECLARE_EXTENDED_PHASE(BEGIN_PDNP);
DECLARE_EXTENDED_PHASE(END_PDNP);

DECLARE_EXTENDED_PHASE(BEGIN_PDNA);
DECLARE_EXTENDED_PHASE(END_PDNA);

DECLARE_EXTENDED_PHASE(BEGIN_SREF);
DECLARE_EXTENDED_PHASE(END_SREF);

// Phases for Power Down Bankwise
DECLARE_EXTENDED_PHASE(BEGIN_PDNPB);
DECLARE_EXTENDED_PHASE(END_PDNPB);

DECLARE_EXTENDED_PHASE(BEGIN_PDNAB);
DECLARE_EXTENDED_PHASE(END_PDNAB);

DECLARE_EXTENDED_PHASE(BEGIN_SREFB);
DECLARE_EXTENDED_PHASE(END_SREFB);


//Triggers
DECLARE_EXTENDED_PHASE(REF_TRIGGER);
DECLARE_EXTENDED_PHASE(PDN_TRIGGER);


#endif

