<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
    <parameter id="memoryId" type="string" value="orgr_16Gb_DDR4_16bit" />
    <parameter id="memoryType" type="string" value="DDR3" />
    <memarchitecturespec>
        <parameter id="width" type="uint" value="16" />
        <parameter id="nbrOfBanks" type="uint" value="8" />
        <parameter id="nbrOfRanks" type="uint" value="1" />
        <parameter id="nbrOfColumns" type="uint" value="1024" />
        <parameter id="nbrOfRows" type="uint" value="131072" />
        <parameter id="dataRate" type="uint" value="2" />
        <parameter id="burstLength" type="uint" value="8" />
    </memarchitecturespec>
    <memtimingspec>
        <parameter id="clkMhz" type="double" value="1200" />
        <parameter id="RC" type="uint" value="52" />
        <parameter id="RCD" type="uint" value="18" />
        <parameter id="RL" type="uint" value="18" />
        <parameter id="RP" type="uint" value="18" />
        <parameter id="RFC" type="uint" value="313" />
        <parameter id="RAS" type="uint" value="34" />
        <parameter id="WL" type="uint" value="12" />
        <parameter id="AL" type="uint" value="0" />
        <parameter id="DQSCK" type="uint" value="0" />
        <parameter id="RTP" type="uint" value="6" />
        <parameter id="WR" type="uint" value="15" />
        <!-- doesn't matter (exit self-refresh) -->
        <parameter id="XP" type="uint" value="4" />
        <parameter id="XPDLL" type="uint" value="13" />
        <parameter id="XS" type="uint" value="64" />
        <parameter id="XSDLL" type="uint" value="512" />
        <!-- -->
        <parameter id="REFI" type="uint" value="2341" />
        <parameter id="CL" type="uint" value="15" />

        <parameter id="FAW" type="uint" value="37" />
        <parameter id="RRD" type="uint" value="8" />
        <parameter id="CCD" type="uint" value="4" />
        <parameter id="WTR" type="uint" value="8" />
        <parameter id="CKE" type="uint" value="8" />
        <parameter id="CKESR" type="uint" value="8" />
    </memtimingspec>
    <mempowerspec>
        <parameter id="idd0" type="double" value="210.5" />
        <!-- doesn't matter (power down) -->
        <parameter id="idd2p0" type="double" value="16.0" />
        <parameter id="idd2p1" type="double" value="55.0" />
        <!-- -->
        <parameter id="idd2n" type="double" value="99.0" />
        <!-- doesn't matter (power down) -->
        <parameter id="idd3p0" type="double" value="70.0" />
        <parameter id="idd3p1" type="double" value="70.0" />
        <!-- -->
        <parameter id="idd3n" type="double" value="115.0" />
        <parameter id="idd4w" type="double" value="1511.4" />
        <parameter id="idd4r" type="double" value="1470.8" />
        <parameter id="idd5" type="double" value="1226.0" />
        <!-- doesn't matter (self-refresh) -->
        <parameter id="idd6" type="double" value="22.0" />
        <!-- -->
        <parameter id="vdd" type="double" value="1.2" />
        <!-- 
             For the paper tests were made with memory type DDR3.
             There was a problem with DDR3 memspec loading discussed in
             https://git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system/issues/202
             In summary, when loading DDR3 specs the values of vdd, idd0 and
             idd6 were assigned to vdd2, idd02 and idd62 (second voltage
             domain).
             The specs provided for testing considered only one voltage
             domain. It was required to treat the DDR3 problem like a feature.
             Since the problem was fixed this specs will not produce the same
             behavior.
             See also:
             https://git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system/pull/203
        -->
    </mempowerspec>
</memspec>
