/*
 * Copyright (c) 2020, Technische Universität Kaiserslautern
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived from
 *    this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Author: Lukas Steiner
 */

#ifndef CHECKERDDR5_H
#define CHECKERDDR5_H

#include <queue>
#include <vector>

#include <DRAMSys/controller/checker/CheckerIF.h>

#include <DRAMSys/configuration/memspec/MemSpecDDR5.h>
#include <DRAMSys/configuration/Configuration.h>
#include <DRAMSys/common/utils.h>

class CheckerDDR5 final : public CheckerIF
{
public:
    explicit CheckerDDR5(const Configuration& config);
    sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
    void insert(Command command, const tlm::tlm_generic_payload& payload) override;

private:
    const MemSpecDDR5 *memSpec;

    std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndDimmRank;
    std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndPhysicalRank;
    std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndLogicalRank;
    std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
    std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
    std::vector<sc_core::sc_time> lastScheduledByCommand;
    sc_core::sc_time lastCommandOnBus;
    TimeInterval dummyCommandOnBus;

    std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankInGroup;

    std::vector<std::queue<sc_core::sc_time>> last4ActivatesPhysical;
    std::vector<std::queue<sc_core::sc_time>> last4ActivatesLogical;

    std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndDimmRank;
    std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndPhysicalRank;
    std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndLogicalRank;
    std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndBankGroup;
    std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndBank;
    std::vector<uint8_t> lastBurstLengthByCommand;

    std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndBankInGroup;

    // TODO: store BL of last RD and WR globally or for each hierarchy?

    sc_core::sc_time cmdLengthDiff;

    sc_core::sc_time tBURST16;
    sc_core::sc_time tBURST32;
    sc_core::sc_time tWTRA;
    sc_core::sc_time tWRRDA;
    sc_core::sc_time tWRPRE;
    sc_core::sc_time tRDAACT;
    sc_core::sc_time tWRAACT;
    sc_core::sc_time tCCD_L_RTW_slr;
    sc_core::sc_time tCCD_S_RTW_slr;
    sc_core::sc_time tCCD_RTW_dlr;
    sc_core::sc_time tRDRD_dpr;
    sc_core::sc_time tRDRD_ddr;
    sc_core::sc_time tRDWR_dpr;
    sc_core::sc_time tRDWR_ddr;
    sc_core::sc_time tCCD_L_WTR_slr;
    sc_core::sc_time tCCD_S_WTR_slr;
    sc_core::sc_time tCCD_WTR_dlr;
    sc_core::sc_time tWRWR_dpr;
    sc_core::sc_time tWRWR_ddr;
    sc_core::sc_time tWRRD_dpr;
    sc_core::sc_time tWRRD_ddr;
    sc_core::sc_time tRDPDEN;
    sc_core::sc_time tWRPDEN;
    sc_core::sc_time tWRAPDEN;
};

#endif // CHECKERDDR5_H
